1. Field of the Invention
The present invention relates generally to a method and arrangement of determining an approximated reciprocal of a divisor, and more specifically to such a method and arrangement wherein a fraction of a divisor is binary normalized and then applied to circuitry for generating an approximated reciprocal of a divisor. The approximated reciprocal thus generated is utilized to obtain a quotient by multiplying it by a dividend. The present invention features an effective reduction of operation time for obtaining binary normalized data.
2. Description of the Prior Art
It is known in the art to obtain a quotient of two binary numbers by determining an approximate reciprocal divisor and multiplying it by a dividend. Such arithmetic algorithms for obtaining a quotient by way of multiplication, has been disclosed in Japanese Laid-Open Patent Specification No. 57-41737 and U.S. Pat. No. 4,047,011, merely by way of example.
Before describing the present invention, a known technique for determining an approximated reciprocal of a divisor will be discussed with reference to FIGS. 1 and 2.
FIG. 1 shows in block diagram form, a known arrangement for determining an approximated reciprocal of a divisor, and FIG. 2 is a table showing part of a fraction of a divisor and outputs of blocks of the FIG. 1 arrangement for describing the FIG. 1 arrangement. In FIG. 2, "X" denotes bits which are not concerned with the operation of the FIG. 1 arrangement.
In FIG. 1, a selector 10 is arranged to receive two kinds of data A and B. The data A is a fraction of a divisor to be applied from external circuitry, while the data B is the output of a shifter 12. The shifter 12 is arranged to binary normalize a fraction of a divisor by left shifting thereof. The selector 10 chooses one of the data A and B in response to a control signal applied from a controller 14. The operations of the controller 14 and the shifter 12 will be described in more detail later.
A register 16 stores one of the data A and B from the selector 10. It should be noted that a fraction of a divisor stored within the register 16 takes a form which starts with a sign bit denoting fraction, "0" being positive and "1" being negative. The subsequent bit positions are occupied by fraction digits (see column B of FIG. 2).
The upper 2 bits of the content of the register 16 are applied to a binary normalization checker 18 which determines whether or not the fraction within the register 16 is binary normalized. The output of the checker 18 is applied to the controller 14.
On the other hand, a predetermined number of upper bits of the fraction stored within the register 16 is applied to a unit 20, which generates an approximated reciprocal of a divisor. However, whether or not a register 22 receives the result obtained by the unit 20 is determined by the controller 14.
Further, the whole fraction within the register 16 is applied to a shift number count unit 24 and also to the binary normalization shifter 12. The unit 24 determines the amount of shifting the fraction to left necessary for binary normalization. Following this, a shifter 12 binary normalizes the fraction applied from the register 16 using the output of the unit 24, and then applies the binary normalized number to the selector 10. It goes without saying that if the fraction within the register 16 is already binary normalized, the unit 24 determines the amount of shifting to be zero. Accordingly, in this instance the shifter 12 is not required to shift the fraction received from the register 16.
It should be noted that the blocks 12, 18, 20 and 24 are always supplied with the corresponding data from the register 16. The controller 14, in response to the output of the binary normalization checker 18, controls the selector 10 and the registers 16, 22. More specifically, in the event that the checker 18 detects that the fraction within the register 16 is not binary normalized, the controller 14 controls the selector 10 to choose the data B and allows the register 16 to receive the output of the selector 10. Further, the controller 14 inhibits the register 22 to receive the output of the unit 20.
It is vital in the FIG. 1 arrangement that data applied to the unit 20 should be binary normalized. This is because, if the unit 20 is not supplied with a binary normalized data, the hardware arrangement of the unit 20 becomes extremely bulky. More specifically, it is assumed that a radix point of a fraction is between the most significant bit (MSB) (namely a sign bit) and the second MSB. Thus, a divisor Y (in 2's compliment) which is binary normalized can be represented as follows: ##EQU1## wherein each parenthesized number denotes a radix. An approximated reciprocal of the binary normalized divisor R (=1/Y) falls within the following ranges:
-2.sub.(10) &lt;R.ltoreq.-1.sub.(10) PA2 1.sub.(10) &lt;R.ltoreq.2(10)
Meanwhile, in the event that a divisor Y is not binary normalized, the integer part of R=1/Y increases infinitely. On the other hand, by way of example, a divisor is assumed to be a normalized hexadecimal data, then the integer part of R=1/Y becomes a finite number. However, if the unit 20 is configured to generate an approximated reciprocal of a normalized hexadecimal, the hardware arrangement of unit 20 becomes very large as compared with the case wherein the unit 20 deals with binary normalized data. This is the reason why the unit 20 should be supplied with binary normalized numbers.
The operation of the FIG. 1 arrangement will be further described with reference to FIG. 2. It is assumed that data to be treated by the FIG. 1 arrangement is binary or hexadecimal floating point data. Whether the data is binary or hexadecimal depends on the program being executed. Consequently, the data stored in the register 16 exhibits 32 variations in the event that the upper 5 bits thereof are considered (see columns A and B of FIG. 2). It should be noted that each of the data shown in FIG. 2 is represented in 2's compliment.
The selector 10 is first supplied, from external circuitry, with a fraction of a divisor. In this instance, the register 16 stores the externally applied fraction of a divisor through the selector 10. Following this, the binary normalization checker 18 receives the upper 2 bits of the content of the register 16, and the unit 20 receives a predetermined number of upper bits of the register 16. Further, both of the shift number count unit 24 and the shifter 12 receive the whole fraction of the register 16. The checker 18 checks to see if the fraction stored in the register 16 is binary normalized or not. It should be noted that the MSB is a sign bit for fraction. The binary normalization check result is applied from the checker 18 to the controller 14 whose output is coupled to the selector 10, the registers 16 and 22. It is assumed for the sake of explanation that the check result assumes a logic 0 in the event the fraction within the register 16 is binary unnormalized, and assumes a logic 1 when the fraction within the register 16 is binary normalized (see column D of FIG. 2).
As shown in column D of FIG. 2, the data No. 1 to 8 and 25 to 32 are not binary normalized, while the data No. 9 to 24 are binary normalized. As is known, determining whether the data is binary normalized or not, is performed by checking to see if the upper 2 bits exhibit the same logic values or not.
In the event the checker 18 determines that the fraction of a divisor within the register 16 is binary normalized, the checker 18 applies a logic 1 to the controller 14. Since the approximate reciprocal divisor generating unit 20 receives a normalized binary data in this case, the controller 14 allows the register 22 to store the approximated reciprocal of a divisor outputted from the unit 20.
On the contrary, if the checker 18 determines that the fraction of a divisor within the register 16 is not binary normalized, the checker 18 applies a logic 0 to the controller 14. In response to the logic 0 applied, the controller 14 controls the selector 10 to choose the data B (viz., the output of the shifter 12). In this instance, the controller 14 inhibits the register 22 to acquire the calculation result fed from the unit 20 as the unit 20 calculates an approximated reciprocal of an unnormalized divisor.
As mentioned previously, the unit 24 receives the whole fraction within the register 16 and determines the amount of left shifting necessary for binary normalization thereof. The operation of the unit 24 is independent of those of the blocks 18 and 20. The unit 24 applies the output thereof to the shifter 12. The shifter 12 binary normalizes (if necessary) a fraction of a divisor in response to the output of the unit 24 (see column E of FIG. 2). The shifter 12 applies the binary normalized data to the selector 10. In the event that the checker 18 detects the fraction stored within the register 16 is not binary normalized, the controller 14 steers the selector 10 to apply the output of the shifter 12 to the register 16 and allows the register 16 to acquire the output of the selector 10. Thereafter, the register 16 again applies the upper 2 bits of the content thereof to the checker 18 and simultaneously applies a predetermined number of upper bits of the content thereof to the unit 20. In this instance, the fraction of a divisor stored in the register 16 is now binary normalized, the checker 18 outputs a logic 1 and the controller 14 allows the output of the unit 20 to be applied to the register 22. In the above description, should the fraction of a divisor be binary normalized, the exponent should be shifted to the left to meet the shifting of the fraction.
It should be noted that even if the fraction of a divisor applied from external circuitry to the selector 10 is a normalized hexadecimal, the possibility that the normalized hexadecimal is also binary normalized is very low. As shown in FIG. 2, the binary unnormalized data comprise about one-half of the thirty two data. In practice, however, this ratio will vary with the data applied to the FIG. 1 arrangement. As will be appreciated, the relatively large amount of binary unnormalized data must be subject to binary normalization using the circuits 24 and 12.
However, the binary normalization using loop 23 requires the normalization of an entire fraction within the register 16 and hence wastes one or two clocks of operation time therefor. Consequently, the prior art techniques shown in FIG. 1 has encountered a problem that a long execution time is inevitably necessary for generating an approximated reciprocal of a divisor.